FIG. 1 is a schematic circuit diagram illustrating a typical display panel. As shown in FIG. 1, the display panel comprises multiple pixel elements 101˜126, which are arranged in an array. Each of the pixel elements 101˜126 comprises a storage unit c101˜c126 and a switch unit m101˜m126. For example, the storage units c101˜c126 are capacitors, and the switch units m101˜m126 are transistors. In addition, the display panel further comprises multiple gate lines g1˜g3 and multiple data lines d1˜d6. When the switch units m101˜m126 are controlled by a gate control unit (not shown), corresponding pixel data are inputted and stored into respective storage unit c101˜c126 via the data lines d1˜d6. As the size of the display panel is increased, there are more pixel elements, gate lines and data lines on the display panel.
Generally, the display panel of FIG. 1 could be applied to an AMOLED (active matrix organic light emitting diode) device or a LCD (liquid crystal display) device.
FIG. 2A is a schematic circuit diagram illustrating a gate line circuit according to the prior art. The gate line circuit comprises a gate driver 230, a gate line 240 and n pixel elements 211˜21n. As shown in FIG. 2A, these pixel elements 211˜21n are enabled or disabled according to the on/off statuses of respective switch units m211˜m21n. Moreover, the output terminal of the gate driver 230 connects to the gate line 240, and the gate line 240 connects to the switch units m211˜m21n. Similarly, the switch units m211˜m2 in are transistors. For controlling the on/off statuses of the switch units m211˜m21n, the gate driver 230 generates a driving signal having alternate high and low levels. When the driving signal is at the high-level state, the switch units m211˜m21n are turned on. Whereas, when the driving signal is at the low-level state, the switch units m211˜m21n are turned off. Generally, the gate control unit of the display panel comprises multiple gate drivers 230. For illustration and brevity, only one gate driver 230 is shown in the drawings.
FIG. 2B is a schematic circuit diagram illustrating an equivalent circuit of the gate line circuit shown in FIG. 2A. As shown in FIG. 2B, the switch units m211˜m21n are equivalent to respective capacitors c1˜cn, and the gate line 240 are equivalent to multiple serially-connected resistors r1˜rn. Since the high-level state and the low-level state of the driving signal are quickly alternated, the rising edge slope and the falling edge slope at the output terminal of the gate driver 230 are very sharp. Whereas, when the driving signal is transmitted to the last (i.e. the nth) switch unit cn, the rising edge slope and the falling edge slope become smoother.
FIG. 2C is a plot illustrating the variations of gate voltages at the first switch unit and the last switch unit of the equivalent circuit shown in FIG. 2B. The curve I indicates the variation of the gate voltage at the first switch unit c1; and the curve II indicates the variation of the gate voltage at the last switch unit cn. After the driving signal is switched from the high-level state to the low-level state for a time period Δt1, the gate voltage at the first switch unit c1 indicates that the first switch unit c1 is completely turned off (see the curve I). On the other hand, the gate voltage at the last switch unit cn is still too high, indicating that the last switch unit cn is not completely turned off (see the curve II). Under this circumstance, a so-called feed-through voltage effect occurs. Due to the feed-through voltage effect, the brightness or the images shown on the display panel are usually inconsistent.
For solving the above drawbacks, a large resistor R is serially connected with the gate line. FIG. 3A is a schematic circuit diagram illustrating another equivalent circuit of the gate line circuit according to the prior art. As shown in FIG. 3A, a large resistor R is connected between the output terminal of the gate driver 230 and the first switch unit c1 in series. In other words, the driving signal will be firstly transmitted across the large resistor R and then transmitted to the first switch unit c1. Since the large resistor R is serially connected to the gate line, the charge/discharge time constant of the first switch unit c1 is increased. When the driving signal is transmitted to the first switch unit c1, the rising edge slop and the falling edge slop of the driving signal become smoother.
FIG. 3B is a plot illustrating the variations of gate voltages at the first switch unit and the last switch unit of the equivalent circuit shown in FIG. 3A. The curve III indicates the variation of the gate voltage at the first switch unit c1; and the curve IV indicates the variation of the gate voltage at the last switch unit cn. After the driving signal is switched from the high-level state to the low-level state for a time period Δt2, the gate voltage at the first switch unit c1 indicates that the first switch unit c1 is completely turned off (see the curve III). On the other hand, the gate voltage at the last switch unit cn also indicates that the last switch unit cn is also completely turned off (see the curve IV). That is, after the driving signal is switched from the high-level state to the low-level state for a time period Δt2, the switch units c1˜cn are almost completely turned off at the same time. Therefore, the brightness or the images shown on the display panel will become more consistent.
FIG. 4 is a schematic circuit diagram illustrating an equivalent circuit of another gate line circuit according to the prior art. As shown in FIG. 4, a large capacitor C is connected between the output terminal of the gate driver 230 and the ground terminal. In other words, the driving signal will be firstly transmitted across the large capacitor C and then transmitted to the first switch unit c1 . Since the large capacitor C is connected to the gate line in parallel, the charge/discharge time constant of the first switch unit c1 is increased. In other words, when the driving signal is transmitted to the first switch unit c1, the rising edge slope and the falling edge slope of the driving signal become smoother.
The gate line circuits as shown in FIGS. 3A and 4, however, still have some drawbacks. For example, the large capacitor C or the large resistor R will occupy a large layout area of the display panel. In addition, the large resistor R will increase the power consumption of the display panel.